[low-temperature polysilicon thin film transistor and fabrication method thereof]

ABSTRACT

An LTPS-TFT structure comprises a gate, a gate dielectric layer, a patterned silicon layer, a patterned insulating layer, an ohmic contact layer and a source/drain layer. The gate and the gate dielectric layer are disposed on the substrate. The patterned silicon layer and the patterned insulating layer are disposed on the gate dielectric layer over the gate. The patterned silicon layer comprises a polysilicon channel region and an amorphous silicon hot carrier restrain region. The ohmic contact layer is disposed on a portion of the patterned silicon layer other than the polysilicon channel region and the amorphous silicon hot carrier restrain region and a portion of the patterned insulating layer over the amorphous silicon hot carrier restrain region. The source/drain layer is disposed on the ohmic contact layer and the gate dielectric layer.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims the priority benefit of Taiwan applicationserial no. 93109432, filed Apr. 6, 2004.

BACKGROUND OF INVENTION

1. Field of the Invention

The present invention relates to a transistor and fabrication methodsthereof, and more particularly to a low-temperature polysilicon thinfilm transistor (LTPS-TFT) and fabrication methods thereof.

2. Description of the Related Art

Generally, devices use switches to control the operation thereof. Forexample, active matrix displays use thin film transistors (TFT) asdriving components. According to the material of a channel layer of theTFT, the types of the TFT include amorphous silicon TFT and polysiliconTFT. Based on the position of the channel layer corresponding to that ofthe gate, the types of TFT also include top-gate TFT and bottom-gateTFT. The bottom-gate TFT has an insulating/amorphous silicon layerinterface which is capable of preventing contamination during process.The fabrication method can also be integrated with the back-channeletching technology. The bottom-gate TFT, therefore, is more popularlyused for the switching devices of liquid crystal displays. Furthermore,compared with the amorphous silicon TFT, the polysilicon TFT has lowpower consumption and high electron mobility. It also gets moreattention in the industry as well.

The prior art method of fabricating the polysilicon TFT requires a hightemperature process up to 1000° C. Due to the high temperaturerequirement, the choice of the substrate material that can be applied tothe process is limited. By the development of laser technology, theprocessing temperature can be substantially down to or under 600° C. Thepolysilicon TFT fabricated by such process is called a low-temperaturepolysilicon TFT (LTPS-TFT). The technology utilizes the laser annealingprocess to melt and recrystalize the amorphous silicon layer intopolysilicon layer. The normally used laser annealing process is theexcimer laser annealing (ELA) process.

Although the polysilicon TFT has the advantages of high carrier mobilityand high driving current about 10⁻⁴ μA, it also creates high leakagecurrent about 10⁻⁹ μA. The polysilicon TFT is easy to induce hot carriereffect at the drain region, causing device degradation. With theconcern, the light doped drain (LDD) region is applied and disposedbetween the channel layer and the source/drain region of the transistorto reduce hot carrier effect.

FIGS. 1A-1E are cross-sectional views showing a method of fabricating aprior art LTPS-TFT. Referring to FIG. 1A, a gate 102, a gate dielectriclayer 104 and an amorphous silicon layer 106 are sequentially formed ona substrate 100. An ELA process is performed to melt and recrystalizethe amorphous silicon layer 106 into a polysilicon layer by the excimerlaser beams 118. Referring to FIG. 1B, the polysilicon layer 106 a ispatterned to form the active region of the thin film transistor.

Referring to FIG. 1C, a silicon oxide layer 108 is formed on thepolysilicon layer 106 a over the gate 102. The silicon oxide layer 108serves as a mask for implantation of ions 130 to form the ohmic contactlayer 110 of the transistor. The polysilicon layer 106 a formed over thegate 102 is the channel layer 112.

Referring to FIG. 1D, another silicon oxide layer 108 a is form on thechannel layer 112. The silicon oxide layer 108 a serves as another maskfor lightly-doping 140 to form the LDD region between the channel layer112 and the ohmic contact layer 110. Referring to FIG. 1E, asource/drain region 116 is formed on the ohmic contact layer 110 and thegate dielectric layer 104 to cover a portion of the silicon oxide layer108 a. Accordingly, a bottom-gate LTPS-TFT 120 is complete.

From the prior art process, at least five masks are required tofabricate the prior art LTPS-TFT 120. In addition, the LDD process is socomplicated that the method of fabricating the prior art LTPS-TFT hashigh manufacturing cost.

SUMMARY OF INVENTION

Accordingly, the present invention is directed to a low-temperaturepolysilicon thin film transistor (LTPS-TFT) to improve deviceperformance by forming an amorphous silicon hot carrier restrain region.

The present invention is also directed to a method of fabricating aLTPS-TFT. The method is capable of reducing manufacturing costs as wellas improving device performance by forming an amorphous silicon hotcarrier restrain region.

The present invention discloses a LTPS-TFT. The LTPS-TFT comprises agate, a dielectric gate, a patterned silicon layer, a patternedinsulating layer, an ohmic contact layer, and a source/drain layer whichare sequentially formed on a substrate. The patterned silicon layer isdisposed on the gate dielectric layer and directly over the gate. Thepatterned silicon layer comprises a polysilicon channel region and anamorphous silicon hot carrier restrain region adjacent thereto. Also,the patterned silicon layer further comprises an edge portion (i.e. aportion of the patterned silicon layer other than the polysiliconchannel region and the hot carrier restrain region) underneath the ohmiccontact layer. The amorphous silicon hot carrier restrain region iscapable of reducing hot carrier effect, preventing degradation of thetransistor during the operation of the transistor. The patternedinsulating layer covers the patterned silicon layer. The ohmic contactlayer is disposed on the edge portion of the patterned silicon layer anda portion of the insulating layer over the amorphous silicon hot carrierrestrain region to expose a portion of the patterned insulating layerand contacting the amorphous silicon hot carrier restrain region. Thesource/drain layer is disposed on the ohmic contact layer, or even on aportion of the substrate.

According to an embodiment of the present invention, the LTPS-TFTfurther comprises a passivation layer disposed on the source/drain layerto cover the insulating layer.

According to an embodiment of the present invention, the ohmic contactlayer comprises a n-type ohmic contact layer or a p-type ohmic contactlayer. In other words, the LTPS-TFT of the present invention can be an-type transistor or a p-type transistor. In an embodiment, the materialof the insulating layer comprises silicon nitride or silicon oxide.

The present invention discloses a method of fabricating a LTPS-TFT.First, a gate is formed on a substrate. A gate dielectric layer isformed on the substrate and the gate. A first amorphous silicon layer, apatterned insulating layer and a second amorphous layer are sequentiallyformed over the gate. The patterned insulating layer is formed on aportion of the first amorphous silicon layer and directly over the gate,and the second amorphous silicon layer is formed on the first amorphousand the patterned insulating layer. The first amorphous silicon layerand the second amorphous silicon layer are patterned to form a firstpatterned amorphous layer and a second patterned amorphous layer toexpose a portion of the gate dielectric layer. The second patternedamorphous silicon layer exposes a portion of the patterned insulatinglayer.

After forming the second patterned amorphous silicon layer, a portion ofthe first patterned amorphous silicon layer is melted and thenrecrystalized to form a polysilicon channel region over the gate. Thefirst patterned amorphous silicon layer under the overlap of the secondpatterned amorphous and the patterned insulating layer becomes anamorphous silicon hot carrier restrain region. A source/drain layer isformed on the second patterned amorphous silicon layer.

The present invention discloses another method of fabricating aLTPS-TFT. First, a gate is formed on a substrate. A gate dielectriclayer is formed on the substrate and the gate. A first amorphous siliconlayer, a patterned insulating layer and a second amorphous layer aresequentially formed over the gate. The patterned insulating layer isformed on a portion of the first amorphous silicon layer and directlyover the gate, and the second amorphous silicon layer is formed on thefirst amorphous and the patterned insulating layer. The first amorphoussilicon layer and the second amorphous silicon layer are patterned toform a first patterned amorphous layer and a second patterned amorphouslayer to expose a portion of the gate dielectric layer. The secondpatterned amorphous silicon layer exposes a portion of the patternedinsulating layer.

After forming the second patterned amorphous silicon layer, asource/drain layer is formed on the second patterned amorphous siliconlayer. The material of the source/drain layer can be, for example, metalor other conductive material. Then a first patterned amorphous siliconlayer is melted and then recrystalized to form a polysilicon channelregion over the gate. The first patterned amorphous silicon layer underthe overlap of the second patterned amorphous and the patternedinsulating layer becomes an amorphous silicon hot carrier restrainregion.

According to the embodiments of the present invention, the method offorming the can be, for example, a laser annealing process. The laserannealing process can be, for example, an excimer laser annealingprocess.

According to an embodiment of the present invention, the method furthercomprises doping the first amorphous silicon layer after forming thepatterned insulating layer and before forming the second amorphoussilicon layer. In another embodiment, the method further comprisesdoping another portion of the first amorphous silicon layer and thesecond amorphous silicon layer in the same process after forming thesecond amorphous silicon layer and before forming the source/drainlayer. In the other embodiment, the method further comprises dopinganother portion of the first patterned amorphous silicon layer and thesecond patterned amorphous silicon layer outside the polysilicon channelregion and the amorphous silicon hot carrier restrain region, afterforming the polysilicon channel region and before forming thesource/drain layer. After performing the doping process, an activationprocess is performed for the first patterned amorphous silicon layer andthe second patterned amorphous silicon layer which are doped, repairingdefects of crystal lattice.

According to the embodiment of the present invention, the firstpatterned amorphous silicon layer and the second patterned amorphoussilicon layer outside the polysilicon channel region and the amorphoussilicon hot carrier restrain region are melted and then recrystalized toform the ohmic contact layer while forming the polysilicon channelregion.

According to the embodiment of the present invention, the method furthercomprises forming a passivation layer over the source/drain layer tocover the insulating layer.

Compared with the prior art method of fabricating LTPS-TFT, thefabrication method of the present invention saves a lightly-doped drain(LDD) process and a LDD mask. The manufacturing cost, therefore, isreduced. Moreover, the LTPS-TFT of the present invention has theadvantages of high driving current of polysilicon thin film transistorsand low leakage current of amorphous thin film transistors.

In order to make the aforementioned and other objects, features andadvantages of the present invention understandable, a preferredembodiment accompanied with figures is described in detail below.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A-1E are cross-sectional views showing a method of fabricating aprior art LTPS-TFT.

FIGS. 2A-2H are cross-sectional views showing progression steps of themethod of fabricating a LTPS-TFT according to the first embodiment ofthe present invention.

FIGS. 3A-3C are cross-sectional views showing partial steps of themethod of fabricating a LTPS-TFT according to the second embodiment ofthe present invention.

FIGS. 4A-4B are cross-sectional views showing partial steps of thefabricating a LTPS-TFT according to the third embodiment of the presentinvention.

FIGS. 5A-5B are cross-sectional views showing partial steps of thefabricating a LTPS-TFT according to the fourth embodiment of the presentinvention.

DETAILED DESCRIPTION

The present invention discloses a low-temperature polysilicon thin filmtransistor (LTPS-TFT) structure with an amorphous region between thechannel region and the source/drain layer. The amorphous region preventshot carrier effect by reducing the impact of high-energy elections,under high electrical field, on the source/drain layer. The LTPS-TFT ofthe present invention can be fabricated by a variety of processes.Following are embodiments of the present invention. The embodimentsillustrate the LTPS-TFT and the fabrication method thereof. The scope ofthe invention, however, is not limited thereto. One of ordinary skill inthe art will understand and modify the structure and process inaccordance with the embodiments. The modification therefrom still fallswithin the scope of the present invention.

FIGS. 2A-2H are cross-sectional views showing progression steps of themethod of fabricating a LTPS-TFT according to the first embodiment ofthe present invention. Referring to FIG. 2A, a gate 202, a gatedielectric layer 204, a first amorphous silicon layer 206 and apatterned insulating layer 208 are sequentially formed on a substrate200. The patterned insulating layer 208 is formed on the first amorphoussilicon layer 206, and over the gate 202. In this embodiment, thematerial of the patterned insulating layer 208 includes, for example,silicon nitride, silicon oxide or other dielectric materials.

Referring to FIG. 2B, the patterned insulating layer 208 serves as amask for an implantation process, such as ion implantation. The dopingions 230 is doped into a portion of the first amorphous silicon layer206, which is not covered by the patterned insulating layer 208 toreduce the resistance thereof. It serves as the ohmic contact layer inthe subsequent process. The doping ions 230 can be n-type or p-typedoping ions. One of ordinary skill in the art understands that the typeof the ions depends on the type of the transistor, such as a n-type or ap-type transistor.

Referring to FIG. 2C, a second amorphous silicon layer 210 is formed onthe first amorphous silicon layer 206 to cover the patterned insulatinglayer 208. The second amorphous silicon layer 210 can be, for example, adoped amorphous silicon layer. The doped amorphous silicon layer 210 canbe, for example, formed by doping and depositing the second amorphoussilicon layer 210 by, for example, a plasma-enhanced chemical vapordeposition, simultaneously. The process is called in-situ dopingprocess.

Referring to FIG. 2D, the first amorphous silicon layer 206 and thesecond amorphous silicon layer 210 are patterned to form a firstpatterned amorphous silicon layer 206 a and a second patterned amorphoussilicon layer 210 a. The first patterned amorphous silicon layer 206 aand the second patterned amorphous silicon layer 210 a expose a portionof the gate dielectric layer 204 and to define the active region of thetransistor. The second patterned amorphous silicon layer 210 a alsoexposes a portion of the patterned insulating layer 208 over the gate202. The method of patterning the first amorphous silicon layer 206 andthe second amorphous silicon layer 210 includes, for example, alithographic process and an etching process.

FIG. 2E illustrates a laser annealing process. The laser annealingprocess of the present invention can be, for example, an excimer laserannealing process. The structure of FIG. 2D is exposed to excimer laserbeams 222 to melt and then recrystalize a portion of the first patternedamorphous silicon layer 206 a to form the polysilicon channel region 212as shown in FIG. 2F.

The second patterned amorphous silicon layer 210 a is regarded as anenergy-absorbing mask for the laser annealing process. Referring toFIGS. 2D-2E, the second patterned amorphous silicon layer 210 a absorbsenergy from the excimer laser beams 222, transforming into the ohmiccontact layer 214 with partial or complete crystallization. The excimerlaser beams 222 are absorbed by the second patterned amorphous siliconlayer 210 a and barely reach the first patterned amorphous silicon layer206 a thereunder. The patterned insulating layer 208 does not absorb theenergy of the excimer laser beams 222. Accordingly, the first patternedamorphous silicon layer 206 a under the patterned insulating layer 208absorbs the energy of the excimer laser beams 222, transforming into apolysilicon channel region 212. Because the first patterned amorphoussilicon layer 206 a under the patterned insulating layer 208 is undoped,the first patterned amorphous silicon layer 206 a under the overlap ofthe second patterned amorphous silicon layer 210 and the patternedinsulating layer 208 becomes an undoped amorphous silicon hot carrierrestrain region 216. The fabrication method of the present inventionprecisely defines the position of the polysilicon region and theamorphous silicon region. Due to the high impedance of the amorphoussilicon, the amorphous silicon hot carrier restrain region 216effectively reduces leakage currents of the transistor. In other words,the leakage current is reduced.

While melting and recrystalizing the amorphous silicon layer to form thepolysilicon layer, the excimer laser annealing process repairs thedefects in the crystal lattice, rearranging the location of atoms toreduce the lattice defects. In this embodiment, the fabrication methodsaves an activation process for repairing lattice.

Referring to FIG. 2G, a source/drain layer 218 is formed on the ohmiccontact layer 214 and the gate dielectric layer 204. The material of thesource/drain layer 218 can be, for example, metal or other conductivematerial. When the method of the present invention is applied in theprocess of fabricating displaying devices, the source/drain layer of thethin film transistor is coupled to the data line of the displayingdevice. The steps of forming the source/drain layer 218 and the dataline can be performed in the same process. The fabrication process,therefore, is simplified.

The LTPS-TFT of the present invention is almost done in FIG. 2G. Afterforming the source/drain layer 218, a passivation layer 220 usually isformed to cover the source/drain layer 218 and the patterned insulatinglayer 208 to protect internal devices of the LTPS-TFT during thefabrication process as shown in FIG. 2H.

In a second embodiment of the present invention, the laser annealingprocess is performed before forming the source/drain layer 218.Following is the description of the second embodiment of the presentinvention.

FIGS. 3A-3C are cross-sectional views showing partial steps of themethod of fabricating a LTPS-TFT according to the second embodiment ofthe present invention. Referring to FIG. 3A, after forming the firstpatterned amorphous silicon layer 206 a and the second patternedamorphous silicon layer 210 a according to the processes of FIGS. 2A-2D,the source/drain layer 218 is formed on the second patterned amorphoussilicon layer 210 a and the gate dielectric layer 204. The secondpatterned amorphous silicon layer 210 a serves as the ohmic contactlayer of the thin film transistor.

Referring to FIG. 3B, the structure formed in FIG. 3A is exposed to theexcimer laser beams 222. During the annealing process, the firstpatterned amorphous silicon layer 206 a above the gate 202 is melted andthen recrystalized, transforming into the polysilicon channel region 212as shown in FIG. 3C. Because of the excellent thermal conductivity ofthe source/drain layer 218, the second patterned amorphous silicon layer210 a and the first patterned amorphous silicon layer 206 a under thesource/drain layer 218 do not absorb the energy of the excimer laserbeams 222. Both ends of the first patterned amorphous silicon layer 206a, which are adjacent to the polysilicon channel region 212 becomes theamorphous silicon hot carrier restrain region 216. The process offorming the passivation layer (not shown) on the source/drain layer 218is optional and depends on the requirement of protecting the transistoror relevant process.

The present invention also comprises doping processes based on therequirement of the process. Following are embodiments illustrating thedoping processes. The elements of the subsequent embodiments, which arethe same as those of the last embodiments, have the materials similarthereto. The detail descriptions are not repeated.

FIGS. 4A-4B are cross-sectional views showing partial steps of themethod of fabricating a LTPS-TFT according to the third embodiment ofthe present invention. Referring to FIG. 4A, after forming the patternedinsulating layer 208 over the substrate 200 in accordance with FIG. 2A,a second amorphous silicon layer 310 is formed on the first amorphoussilicon layer 206 to cover the patterned insulating layer 208. Thesecond amorphous silicon layer 310 can be, for example, a doped or anundoped amorphous silicon layer.

Referring to FIG. 4B, a first patterned amorphous silicon layer 206 aand a second patterned amorphous silicon layer 310 a are formedaccording to the description of FIG. 2D. The patterned insulating layer208 serves as a mask for an implantation process to implant ions 230into the first patterned amorphous silicon layer 206 a and the secondpatterned amorphous silicon layer 310 a. The subsequent processes aresimilar to those of the last embodiments.

In the fourth embodiment, a laser annealing process is performed priorto the doping process of the third embodiment. Following is thedescription of the fourth embodiment.

Referring to FIG. 5A, after forming the structure in FIG. 4A, an excimerlaser annealing process with excimer laser beams 222 is performed tomelt and then recrystalized a portion of the first patterned amorphoussilicon layer 206 a transforming into the polysilicon channel region 212shown in FIG. 5B. Similar to the first embodiment, the second patternedamorphous silicon layer 310 a, during the laser annealing process,absorbs the energy of the excimer laser beams 222, transforming into thepatterned polysilicon layer 311 shown in FIG. 5B.

Referring to FIG. 5B, an implantation process is performed to implantions 230 into the patterned polysilicon layer 311 and the firstamorphous silicon layer 206 a uncovered by the patterned insulatinglayer 208 for forming the ohmic contact layer 214 and the hot carrierrestrain region 216 adjacent to the polysilicon channel region 212,respectively, as shown in FIG. 2F.

In this embodiment, because the implantation process is performed afterthe laser annealing process, an activation process (not shown) isrequired to repair the lattice defects in the ohmic contact layer 204and the first patterned amorphous silicon layer 206 a thereunder. Afterthe activation process, the subsequent processes are similar to those oflast embodiments.

The power of the laser beams applied in the present invention is for thepurpose of forming the polysilicon channel region. For such purpose, thelaser beams applied in the present invention should not penetratethrough the second patterned amorphous silicon layer. Even the power ofthe laser beam just melts and then recrystalizes the surface siliconatoms of the second patterned amorphous silicon layer. Accordingly, theohmic contact layer of the present invention comprises amorphous siliconand crystallized silicon.

The present invention discloses various methods of fabricating theLTPS-TFT in FIG. 2H. One of ordinary skill in the art may choose one ofthem to fabricate a transistor similar to that of the present invention.Following is the detail description of the structure of the LTPS-TFT400. The methods of fabricating the transistor are described in the lastembodiments. Detail descriptions are not repeated.

Referring to FIG. 2H, the LTPS-TFT 400 of the present inventioncomprises the substrate 200 and the structure thereon. The structurecomprises: the gate 202, the gate dielectric layer 204, the patternedinsulating layer 208, the patterned silicon layer 206 a, the ohmiccontact layer 214, the source/drain layer 218 and the passivation layer220. The gate 202 and the gate dielectric layer 204 are sequentiallydisposed on the substrate 200. The patterned silicon layer 206 a isdisposed on the gate dielectric layer 204. The patterned silicon layer206 a comprises a polysilicon channel region 212 over the gate 202 andthe hot carrier restrain region 216 adjacent thereto. Also, thepatterned silicon layer 206 a further comprises an edge portion 402(i.e. a portion of the patterned silicon layer 206 a other than thepolysilicon channel region 212 and the hot carrier restrain region 216)underneath the ohmic contact layer 214. The patterned insulating layer208, which can be, for example, silicon oxide or silicon nitride isdisposed on the patterned silicon layer 206 a.

The ohmic contact layer 214 is disposed on the edge portion of thepatterned silicon layer 206 a and a portion of the patterned insulatinglayer 208 over the amorphous silicon hot carrier restrain region 216 toexpose the patterned insulating layer 208 over the polysilicon channelregion 212. The ohmic contact layer 214 comprises, for example, a n-typeohmic contact layer or a p-type ohmic layer.

The source/drain layer 218 is disposed on the ohmic contact layer 214and the gate dielectric layer 204. The passivation layer 220 is disposedon the source/drain layer 218 and the patterned insulating layer 208,protecting the internal devices of the LTPS-TFT 400 from damage duringsubsequent processes.

Therefore, the present invention has following advantages:

-   1. Compared with the prior art method of fabricating LTPS-TFT, the    fabrication method of the present invention saves a lightly-doped    drain (LDD) process and a LDD mask. The manufacturing cost,    therefore, is reduced.-   2. During the process of fabricating the LTPS-TFT of the present    invention, the second patterned amorphous silicon layer serves as an    energy-absorbing mask for the laser annealing process. Such    amorphous layer precisely defines the amorphous silicon region and    the polysilicon region.-   3. The amorphous silicon hot carrier restrain region enforces the    growth of the crystal from the ends of the polysilicon channel    region towards the center thereof. The uniformity of the grain size    of the polysilicon channel region is improved.-   4. The LTPS-TFT of the present invention has the advantages of high    driving current I_(ON) of polysilicon thin film transistors and low    leakage current I_(OFF) of amorphous thin film transistors. The    transistor has high I_(ON)/I_(OFF) ratio and improves the electrical    performance of the LTPS-TFT.-   5. It is feasible to modify production lines of amorphous silicon    transistor for fabricating LTPS-TFT. The manufacturing cost,    therefore, is substantially reduced.

Although the present invention has been described in terms of exemplaryembodiments, it is not limited thereto. Rather, the appended claimsshould be constructed broadly to include other variants and embodimentsof the invention which may be made by those skilled in the field of thisart without departing from the scope and range of equivalents of theinvention.

1. A low-temperature polysilicon thin film transistor (LTPS-TFT),adapted to be disposed on a substrate, the LTPS-TFT comprising: a gatedisposed on the substrate; a gate dielectric layer disposed on thesubstrate and the gate; a patterned silicon layer disposed on the gatedielectric layer and over the gate, wherein the patterned silicon layercomprises a polysilicon channel region and an amorphous silicon hotcarrier restrain region adjacent thereto; a patterned insulating layerdisposed on the patterned silicon layer; an ohmic contact layer disposedon a portion of the patterned silicon layer other than the polysiliconchannel region and the amorphous silicon hot carrier restrain region anda portion of the insulating layer over the amorphous silicon hot carrierrestrain region to expose a portion of the patterned insulating layer;and a source/drain layer disposed on the ohmic contact layer.
 2. TheLTPS-TFT of claim 1, further comprising a passivation layer disposed onthe source/drain layer to cover the patterned insulating layer.
 3. TheLTPS-TFT of claim 1, wherein the ohmic contact layer comprises an n-typeohmic contact layer or a p-type ohmic contact layer.
 4. The LTPS-TFT ofclaim 1, wherein the material of the insulating layer comprises siliconoxide or silicon nitride.
 5. A method of fabricating a LTPS-TFT,comprising: forming a gate on a substrate; forming a gate dielectriclayer on the substrate and the gate; forming a first amorphous siliconlayer, a patterned insulating layer and a second amorphous layer overthe gate sequentially, wherein the patterned insulating layer is formedon a portion of the first amorphous silicon layer and over the gate, andthe second amorphous silicon layer is formed on the first amorphous andthe patterned insulating layer; patterning the first amorphous siliconlayer and the second amorphous silicon layer to form a first patternedamorphous layer and a second patterned amorphous layer to expose aportion of the gate dielectric layer, wherein the second patternedamorphous silicon layer exposes a portion of the patterned insulatinglayer; melting and then recrystalizing a portion of the first patternedamorphous silicon layer to form a polysilicon channel region over thegate, wherein the first patterned amorphous silicon layer under anoverlap of the second patterned amorphous and the patterned insulatinglayer becomes an amorphous silicon hot carrier restrain region; andforming a source/drain layer on the second patterned amorphous siliconlayer.
 6. The method of fabricating a LTPS-TFT of claim 5, wherein thestep of forming the polysilicon channel region further comprisesperforming a laser annealing process.
 7. The method of fabricating aLTPS-TFT of claim 6, wherein the laser annealing process comprises anexcimer laser annealing process.
 8. The method of fabricating a LTPS-TFTof claim 5, wherein further comprising doping a portion of the firstamorphous silicon layer after forming the patterned insulating layer andbefore forming the second amorphous silicon layer.
 9. The method offabricating a LTPS-TFT of claim 5, wherein further comprising dopinganother portion of the first amorphous silicon layer and the secondamorphous silicon layer after forming the second amorphous silicon layerand before forming the source/drain layer.
 10. The method of fabricatinga LTPS-TFT of claim 9, wherein further comprising doping the anotherportion of the first patterned amorphous silicon layer and the secondpatterned amorphous silicon layer after forming the polysilicon channelregion and before forming the source/drain layer.
 11. The method offabricating a LTPS-TFT of claim 10, wherein further comprisingperforming an annealing activation process for the another portion ofthe first amorphous silicon layer and the second patterned amorphoussilicon layer after doing the another portion of the first amorphoussilicon layer and the second patterned amorphous silicon layer andbefore forming the source/drain layer.
 12. The method of fabricating aLTPS-TFT of claim 5, further comprising forming a passivation layer overthe source/drain layer to cover the insulating layer.
 13. The method offabricating a LTPS-TFT of claim 5, further comprising melting and thenrecrystalizing the second patterned amorphous silicon layer whileforming the polysilicon channel region.
 14. A The method of fabricatinga LTPS-TFT, comprising: forming a gate on substrate; forming a gatedielectric layer on the substrate and the gate; forming a firstamorphous silicon layer, a patterned insulating layer and a secondamorphous layer over the gate sequentially, wherein the patternedinsulating layer is formed on a portion of the first amorphous siliconlayer and over the gate, and the second amorphous silicon layer isformed on the first amorphous and the patterned insulating layer;patterning the first amorphous silicon layer and the second amorphoussilicon layer to form a first patterned amorphous layer and a secondpatterned amorphous layer to expose a portion of the gate dielectriclayer, wherein the second patterned amorphous silicon layer exposes aportion of the patterned insulating layer; forming a source/drain layeron the second patterned amorphous silicon layer; and melting and thenrecrystalizing a portion of the first patterned amorphous silicon layerto form a polysilicon channel region over the gate, wherein the firstpatterned amorphous silicon layer under an overlap of the secondpatterned amorphous and the patterned insulating layer becomes anamorphous silicon hot carrier restrain region.
 15. The method offabricating a LTPS-TFT of claim 14, wherein the step of forming thepolysilicon channel region further comprises performing a laserannealing process.
 16. The method of fabricating a LTPS-TFT of claim 15,wherein the laser annealing process comprises an excimer laser annealingprocess.
 17. The method of fabricating a LTPS-TFT of claim 14, whereinfurther comprising doping another portion of the first amorphous siliconlayer after forming the patterned insulating layer and before formingthe second amorphous silicon layer.
 18. The method of fabricating aLTPS-TFT of claim 14, wherein further comprising doping another portionof the first amorphous silicon layer and the second amorphous siliconlayer after forming the second amorphous silicon layer and beforeforming the source/drain layer.
 19. The method of fabricating a LTPS-TFTof claim 18, further comprising performing an annealing activationprocess for the another portion of the first amorphous silicon layer andthe second patterned amorphous silicon layer after doing the anotherportion of the first amorphous silicon layer and the second patternedamorphous silicon.